Error-correcting systems



9 Sheets-Sheet 4 Filed May 15, 1961 1964 F. M. GOETZ ERROR-CORRECTINGSYSTEMS 9 Sheets-Sheet 5 Filed May 15, 1961 INVENT'OR By F. MEGOETZ A 7'rokNz y in Q HUD kwkfiuwk kkiw .QQRTE 3. Sn mi an -w En 9Q out .63 wu 3mm QNQ van 9 Sheets-Sheet 6 Filed May 15, 1961 QQQOQQOQQQ XXXX'F/AIIII/ENTOR BY 6 GOETZ A T TORNFV 9 Sheets-Sheet 9 Filed May 15, 1961AT TORNE Y United States Patent 3,155,818 ERROR-CORRECTING SYTEMS FrankM. Goetz, Franklin Square, N.Y., assignor to Bell TeiephoneLaboratories, Incorporated, New York, N.Y., a corporation of New YorkFiled May 15, 1961, Ser. No. 110,142 17 Gaines. (Cl. 235-153) Thisinvention relates to digital information processing systems, and moreparticularly to the automatic correction of errors in such systems.

The problem of correctly transmitting binary signals over a noisychannel is a significant one whose solution has been actively sought.Some illustrative situations in which this problem arises are: whentelephone lines subject to error impulses are being used to transmitdata in binary form; when an imperfect medium such as magnetic tape or aphotographic emulsion is used to store binary data; or when operationson binary signals are being carried out by means of circuits constructedof devices such as relays, diodes, or transistors, which have aprobability of error.

In a typical information processing system, care must be taken to ensurethat the transmitter and receiver thereof stay in synchronism. Withoutsome synchronizing scheme the receiver might start decoding at the wronginstant and, as a result, emit only gibberish.

The occurrence of errors in a typical information processing system mayarise from noise impulses which directly alter the digits of atransmitted word. Also, errors in such a system may arise from noiseimpulses which indirectly alter the correspondence between the encodedand decoded words by throwing the encoder and decoder out ofsynchronisum.

An object of the present invention is the improvement of theerror-correcting capabilities of a digital information processingsystem.

More specifically, an object of this invention is an errorcorrectingsystem in which the number of redundant digits required to be added toan information word is relatively small in view of the error-correctingcapabilities of the system.

Another object of the present invention is a reliable and easilyimplementable digital information processing system which isself-correcting with respect to various types of multiple errors.

These and other objects of the present invention are realized in anillustrative system embodiment thereof which comprises a source thatsupplies information words to an encoder, the encoder converting theinformation words into modified words containing suflicient redundancyto permit the words to be slightly mutilated by a noisy channel andstill be correctly interpreted by a decoder. The modified words are sentvia the noisy channel to the decoder, which reconstructs the originalinformation words if the mutilation has not been excessive.

In the encoder of the illustrative system a group of r parity checkdigits are suffixed to each group of n digits which form an informationword, the information digits being initially inserted into the stages ofa main shift register. The check digits are formed by successivelycombining, in an EXCLUSIVE-OR circuit, the digits of a coding sequencewith the information digits appearing in at least one of the stages ofthe main shift register. The coding sequence includes at least one 0 andone 1 and is generated by an auxiliary shift register whose output stageis connected to an input of the EXCLUSIVE-OR circuit. In this way botheven and odd parity relationships are established between theinformation and check digits.

An encoded redundant information word is coupled in a serial mode fromthe terminal output stage of the main "ice shift register to atransmission channel which is subject to error impulses. Synchronizationdigits, which occur in a predetermined time relationship with respect tothe information digits, are also coupled to the channel.

The error-correcting capabilities of one specific system embodiment ofthe principles of the present invention encompass all so-called Class-lerrors, viz., all end-connected loss-bursts or gain-bursts, where thesum of the individual burst lengths is E. In this illustrative systemthe EXCLUSIVE-OR circuit included in the encoder receives as inputsthereto the coding sequence output of the auxiliary shift register andthe information digits appearing in the terminal output stage of themain shift register.

In the decoder of the Class-1 error-correcting system a centered groupof n+r-E digits is obtained. Subsequently, s parity checks are derivedfrom the centered group, these parity checks forming a subsequence ofthe shift register coding sequence employed in the encoding process, thesubsequence being positionable within the shift register sequence inonly one way. In the process of locating the position of the subsequencewithin the sequence the decoding circuitry reconstructs allerroneouslyreceived digits and re-establishes synchronization betweenthe encoded and decoded information digits.

The error-correcting capabilities of a second specific system embodimentof the principles of the present invention encompass Class-1 errors and,in addition, all interior (i.e., not end-connected) loss-bursts oflength E. In this second or Class-2 system the EXCLUSIVE- OR circuitincluded in the encoder receives as inputs thereto the coding sequenceoutput of the auxiliary shift register and the output of anotherEXCLUSIVE-OR circuit whose inputs are information digits appearing inspaced stages of the main shift register.

The decoder of the Class-2 error-correcting system ineludes circuitryfor recognizing Whether an end-connected or an interior error burstoccurred. If an end-connected error occurred, a decoder of the Class-1type is employed to decode the received message. If, ,on the other hand,an interior error is detected, another type of arrangement is employedto perform the decoding operation. This decoding arrangement includes amain shift register through which information and check digits areshifted in such a manner that at each shift the new digit applied to theinput end of the register is derived either from a delay line storingreceived information digits or, in the event that an interior digiterror is detected, from a parity reconstruction circuit.

It is a feature of the present invention that a selfcorrectinginformation processing system include circuitry for establishing botheven and odd parity relationships between the information and checkdigits of the system.

It is another feature of this invention that a self-correcting paritycheck system include encoding circuitry for suflixing a parity checkgroup to an information Word, the circuitry comprising an EXCLUSIVE-ORcircuit whose successive pairs of inputs are the output of a codingsequence generator and a signal derived from at least one of the digitsof the information word.

It is still another feature of the present invention that aself-correcting transmission system include decoding circuitry fordetecting the nature of the mutilation of a transmitted redundant wordand for reconstructing all erroneously-received information digitsthereof.

A complete understanding of the present invention and of the above andother objects, features, and advantages thereof may be gained from aconsideration of the following detailed description of two illustrativeembodiments thereof presented hereinbelow in conjunction with theaccompanying drawing, in which:

FIG. 1 is a generalized depiction of a shift register sequence generatorof the type included in the encoders of illustrative embodiments of theprinciples of the present invention;

FIG. 2 is a tabular listing indicating which switches of the onesrepresented in FIG. 1 are to be closed as the number of stages of theshift register of FIG. 1 is varied from 2 through 20;

FIG. 3 is a tabular listing indicating in part the sequences that anarrangement of the type shown in FIG. 1 is capable of generating;

FIG. 4A is a particularized showing of a four-stage shift registersequence generator of the type shown in FIG. 1;

FIG. 4B is a simplified version of the generator of FIG. 4A;

FIG. 5 depicts the encoder of a specific illustrative Class-1error-correcting system embodying the principles of the presentinvention;

FIG. 6 shows a 30-digit synchronization word and, in addition, aspecific illustrative -digit information word and the IO-digit paritycheck group which is generated and sufiixed to the information word bythe encoder depicted in FIG. 5;

FIG. 7A is a generalized showing of a shift register circuit of the typeincluded in illustrative Class-1 and Class-2 decoders embodying theprinciples of the present invention;

FIG. 7B is a symbolic depiction of the circuit of FIG. 7A;

FIG. 8 shows the decoder of a specific illustrative Class-1error-correcting system made in accordance with the principles of thepresent invention;

FIG. 9 is a tabular listing of the various representations which arestored in the register 300 of FIG. 8 during the decoding operation;

FIG. 10 lists various representations which are stored in the register801 of FIG. 8 during the decoding operatron;

FIG. 11 lists in part the various subsequences which are generated bythe specific illustrative decoder shown in FIG. 8;

FIG. 12 depicts a specific Class-2 encoder made in accordance with theprinciples of the present invention;

FIGS. 13A and 13B depict for comparison purposes for Class-1 and Class-2error-correcting systems, respectively, the configuration of a portionof the decoding circuitry thereof; and

FIG. 14 shows one unit of a specific illustrative Class-2 decoder madein accordance with the principles of the present invention.

Before proceeding to a detailed description of specific illustrativeembodiments of the principles of the present invention, there ispresented hereinbelow certain general introductory and explanatorymaterial of a background nature which is considered helpful to acomplete and clear understanding of the invention. Following thatmaterial, two illustrative system embodiments of the principles of thisinvention are described in detail.

First, a few general words with respect to the type of overall system inwhich the herein-described inventive principles may be embodied and thetype of multiple errors which embodiments of the present invention arecapable of automatically correcting. The inventive concepts areillustratively presented herein in the context of a system in which anencoder and a decoder are interconnected by a channel for transmittingtherebetween information and check digits and synchronization digits. Inthe simplest case, this can be accomplished by means of two separatetransmission lines interconnecting the encoder and decoder. Herein thesetwo lines will be respectively designated the information-carrying lineand the synchronization line. Normally, the synchronization line carriesa pulse or 1 signal in every digit position corresponding in time to theposition in which a digit of the redundant word appears on theinformation-carrying line. Thus, for example, if some -digit word 1001101,

consisting of both information and check digits, appears on theinformatiomcarrying line in digit positions 1 through 30, there ispropagated along the synchronization line during the same time intervala 30-digit word 11111 11, consisting only of 1 signals.

Class-l errors are end-connected loss-bursts or gainbursts, where thesum of the individual burst lengths is E. For the assumed case of aSO-digit word, E would be 7 digits. Whenever the terms lost and gainedare employed herein with respect to digits, it is to be undcrstood thatsuch reference is with respect to the digits of a synchronization word.It is to be noted, however, that impulses which cause errors to occur inthe digits of a synchronization word may also cause errors to occur incorresponding information and check digits appearing on theinformation-carrying line. However, whether or not the correspondingdigits on the information-carrying line are also attected, Class-1errors would result in the encoded and decoded words not being exactreplicas of each other, due to the loss of synchronization therebetween.

More specifically, Class-1 error bursts might, for example, cause theassumed ZO-digit synchronization word to lose as many as 7 consecutivels of its extreme lefthand digits, or as many as 7 consecutive ls of itsextreme right-hand digits. Alternatively, by way of further example, 3extreme left-hand 1s and 4 extreme righthand ls might be lost. Or, suchnoise bursts might, for example, cause as many as 7 consecutive Is to beprefixed or suffixed to the normal synchronization word, or might,illustratively, add 3 consecutive ls as a prefix and 4 consecutive ls asa suffix to the synchronization word.

Class-1 errors occur in those communication systems in which thebeginnings and ends of binary sequences are susceptible to error. Forexample, in a system in which a sequence of pulses is transmittedthrough a filter, the

' first few pulses transmitted therethrough may, due to delay in theresponse characteristic of the filter, be of a lower amplitude thanpulses occurring in the middle of the sequence. Similarly, energystorage effects in the filter may cause additional pulses to be added tothe end of the desired sequence.

Class-2 errors include all Class-1 errors and, in addition, includeinterior loss-bursts of length E. Again, for the assumed case of a30-digit word, E would have the value 7. It is assumed herein thatinterior loss-bursts cause errors to occur both in the digits of asynchronization word and in the corresponding digits of the informationword associted therewith.

For the sake of completeness, it is noted that my copending applicationSerial No. 110,143, filed concurrently herewith, is directed to a systemcapable of correcting so called Class-3 errors, which include bothClass-1 and Class-2 errors and, in addition, the type of error as aresult of which the synchronization digits are unaffected but variousones of the information and check digits are changed in value.

In the systems described herein an encoded redundant word includes Nbinary digits, the first n of which are information digits and theremaining r of which are parity check digits. The number of check digitsis determined by the relationship and the values of the check digits aredetermined by a shift register sequence which establishes both even andodd parity relationships between the information and check digits.

It is noted that the concept of parity and its applicability to thefield of error detection and correction is described in Error Detectingand Error Correcting Codes, R. W.

Iamrning, The Bell System Technical Journal, Volume 29, 1950, pages147160.

The parameter E is employed herein to characterize the burst-correctingproperties of the illustrative system,

embodiments of the principles of the present invention. The systems areself-correcting for error bursts of length E digits, where the burstlength is the distance in digits between and including the first andlast digits affected by a noise burst.

In these illustrative systems each transmitted redundant word must befollowed by a blank interval of at least E-l-l digit intervals, and theminimum word length N is ZE-l-l. These systems are capable of correctingerror bursts of the Class-1 and Class-2 type if adjacent error burstsare separated by at least E-l-l blank intervals or NE correctly-receiveddigits.

An understanding of the type of binary signal sequence known as a shiftregister sequence is essential to an understanding of the principles ofthe illustrative embodiments described herein, for such sequences areintimately related to the encoding and decoding operations performed bythese embodiments. Such a sequence is generated by an arrangement whichincludes a shift register. A shift register sequence (1:11 q q of lengthr and of characteristic s is one in which all continuous subsequences ofs digits are distinct. For any s there always exists such a sequence ifr satisfies the expression A circuit of the generalized form shown inFIG. 1 is employed to generate such shift register sequences.

r and s in expression (2) correspond respectively to the number ofparity check digits to be added during the encoding process to a groupof information digits and to the length of the subsequence by means ofwhich error correction is effected during the decoding operation. Thelength of the subsequence s is determined by the expression FIG. 1includes a plurality of bistable circuits, for example, flip-flops,designated F F F F P P F the initial representation of each of which isindicated by a 1 or a 0 in the upper right-hand corner of the blocksymbol thereof. Connected to each bistable circuit through a switch isan EXCLUSIVE-OR or modulo 2 adder circuit. It is noted that the termsEXCLUSIVE OR and modulo 2 adder are functionally equivalent and areemployed interchangeably herein.

To construct the encoder of a system having an error-correctingcapability B, it is necessary to select a particular shift registersequence generator of the generalized form shown in FIG. 1. For aparticular E the number R of bistable circuits to be included in theshift register is s-l-l, and the switches to be closed for R values of 2through 20 are specified in tabular form in FIG. 2.

FIG. 3 lists in tabular form the shift register sequences which aregenerated by a circuit of the form shown in FIG. 1 for E values of 1through 15. Each of these sequences is obtained by supplying E+s shiftpulses to the arrangement depicted in FIG. 1.

To specifically illustrate the procedure that would be followed indesigning a shift register sequence generator, of the generalized formdepicted in FIG. 1, for inclusion in a particular encoder embodying theprinciples of the present invention, assume that it is desired totransmit 20-digit information words via a noisy channel which is subjectto end-connected or interior error bursts of length 7 digits. In otherterms, It equals 20 and E equals 7. r, the number of partity checkdigits to be sufiixed to each 20-digit information word, is found fromexpression (1) to be equal to 10. s is determined from expression (3) tobe equal to 3, and R, the number of bistable circuits to be included inthe shift register sequence generator, is equal to s-l-l or 4. For an RValue of 4, FIG. 2 indicates that only SW and SW of the switchesincluded in the arrangement of FIG. 1 are to be closed. The resultingshift register sequence generator is shown in FIG. 4A and in moresimplified form in FIG. 4B,

6 wherein the functionless one-input EXCLUSIVE-OR circuits E and E ofFIG. 4A are omitted.

Referring now to FIG. 5, there is shown the encoder of a specificClass-1 error-correcting system which illustratively embodies theprinciples of the present invention. The depicted encoder is designed toconvert 20- digit information words into 30-digit redundant words fortransmission over a noisy channel which is subject to endconnected errorbursts of length 7. Note that the encoder of FIG. 5 includes within thedashed line box thereof a shift register sequence generator 500 of theform described above and shown in FIG. 4B. The component circuits out ofwhich the Class-1 encoder is formed are well known in the art andcompletely conventional, and are accordingly not depicted in detail inthe drawing.

The illustrative Class-l encoder shown in FIG. 5 in cludes a source 505of information words which are to be coupled to a channel fortransmission to a remote location. The source 505 is connected to the 20bistable circuits F F F F of a main shift register 510 and suppliesinformation words thereto under the control of a master timing circuit515.

The information digits stored in the main shift register 510 are shiftedin a serial mode under control of a source 520 of shift pulses throughthe terminal output stage F of the register 510 to aninformation-carrying line 525. Additionally, the information digitstored in the terminal output stage F is coupled to one input of anEXCLUSIVE-OR circuit 536 Whose other input is the shift registersequence output of the generator 500, the serial output sequence of thegenerator 500 also being controlled by the source 520. The modulo 2 sumof the inputs to the circuit 530 is applied to the last stage F of theregister 510.

More specifically, during the IO-digit interval in which the first 10digits of the information word are being shifted to theinformation-carrying line 525, the circuit 530 serially receives fromthe generator 500 via lead 535 a IO-digit sequence containing both 0sand ls and serially receives from the terminal output stage F via lead540 the first 10 digits of the information word. In this way the circuit530 generates, during the noted 10- digit interval, 10 parity checkdigits which are serially coupled vial lead 545 to, the stage F of themain shift register 510. The check digits are subsequently shiftedthrough the register 510 under control of the source 520 and are appliedto the information-carrying line 525 as a 10-digit suffix to the20-digit information word.

During each of the 30 digit positions in which information and checkdigits are being transferred from the terminal output stage F of themain shift register 510 to the information-carrying line 525, the mastertiming circuit 515 couples a 1 signal to a synchronization line 559.Thus, in each 30-digit word period a redundant information wordconsisting of 0s and 1s appears on the information-carrying line 525 anda synchronization word consisting only of 1s" appears on thesynchronization line 550. I It takes 30 shift pulses to transfer a30-digit redundant word to the information-carrying line 525. Encodingof the next information word can begin at any time after the last digitof the previous redundant word has been so transferred. Actual transferof the first digit of the next word to the line 525 must not, however,begin until at least E+l or 8 digit intervals elapse after the transferto the line 525 of the last digit of the previous word.

If the shift register sequence generator of a Class-1 encoder generatesa sequence q=q g q any information word x x x can be encoded inaccordance with the principles of the present invention by satisfyingthefollowing equations:

x +x =q (modulo 2); i=1, 2 r (4) For the specific Class-1 encoderillustrated in FIG. 5, r equals 10, n equals 20, and q equals0001011100.

Thus, if the first information digit x has the value 1, the firstequation of set (5) specifies that x should also be 1. In other words,the first equation of set (5) specifies an even parity relationshipbetween the information digit x and the check digit x that is, thenumber of ls in digit positions x and x is either zero or two. On theother hand, every expression of set (5) which is equal to l specifies anodd parity relationship between the information and check digitsincluded in the expression.

The requirement of the first equation of set (5) is satisfied by theEXCLUSIVE-OR circuit 530 of FIG. 5, for if the input applied to thecircuit 530 on the lead 535 is (which is the first digit of the shiftregister sequence 0001011100) and the input applied thereto on the lead540 is 1 (which is the signal appearing in position x the output of thecircuit 530 is a 1 signal. This 1 signal is the 21st digit of theencoded redundant word and is coupled to the stage F of the main shiftregister 510 after the first information digit of the redundant word hasbeen shifted to the information-carrying line 525. In a similar manner,the circuit 530 generates the other check digits which appear inpositions x through x imposing in each instance an even or an odd parityrelationship between the check digit and its associated informationdigit depending, respectively, 'on whether the digit coupled from thegenerator 500 to the EXCLUSIVE- OR circuit 530 is a 0 or a 1.

In summary, the specific Class-1 encoder depicted in FIG. 5 modifies a20-digit information word by suifixing thereto a -digit parity checkgroup which is generated by an EXCLUSIVE-OR circuit each of whosesuccessive pairs of inputs comprises a digit of a shift registersequence including both 0s and 1s" and the information digit stored inthe terminal output stage of a main shift register. The values of thecheck digits to be added to an information word can be determined fromthe equations of set (5). Thus, for example, it can be readily verifiedthat the encoder of FIG. 5 modifies the -digit information word10001000100010001000, wherein the extreme lefthand 1 appears in digitposition x and the extreme right-hand 0 appears in digit position x bysuflixing thereto the 10-digit check group 0001100000, wherein theextreme left hand 0 appears in digit position x and the extremeright-hand 0" appears in digit position x thereby providing a redundantinformation word of the form shown in FIG. 6. In FIG. 6 the digitsappearing in the positions designated x through x are informationdigits, the digit in position x being the first one thereof to betransferred to the information-carrying line, and the digits appearingin the positions designated x through x are the parity check digits ofthe redundant word.

It is significant to note that the novel encoding principles embodied inthe specific Class-1 circuitry illustrated in FIG. 5 result in thecircuiu'y being able to encode information words in a minimallyredundant manner.

In a Class-1 error-correcting system, decoding is accomplished bycircuitry which (1) counts the number m of consecutively-receiveddigits; (2) selects from the msequence a centered group of N E digits;(3) derives from the centered group a subsequence of s parity checkdigits by means of which the relative position of the NE digits withrespect to the encoded redundant word is indicated; and (4) reconstructsall mutilated digits that are within the error-correcting capabilitiesof the system.

A more analytical description of the decoding procedure carried out by aClass-1 decoder is helpful to a thorough understanding of the principlesof the present invention.

Such a description follows. Let y y y represent a group of digits whichis received from a noisy channel. The N E centered digits of thereceived group may be represented by the expression The sequence 2 p 2is a subsequence of the shift register sequence q q q and can be locatedwithin that sequence in only one way, for, as specified above inconnection with the description of the Class-1 encoder, all continuoussubsequences of s digits in the shift register sequence q q q aredistinct. Let

Then, the information digits involved in the checks from which 1 p p,are derived are, according to Equations 4,

where O j E. Hence, expression (6) can be represented To calculate thevalues x x can be solved as follows:

1=q1+ t+n; 2 j Then, because of the correspondence between expressions(6) and (11), the decoded information word can be represented asfollows:

Next, an illustrative Class-l decoder will be described in detail.Following that description, there will be demonstrated in specific termsthe manner in which the illustrative decoder is capable of automaticallyreconstructing a mutilated redundant information word.

With two exceptions, the component circuits out of which the Class-ldecoder are formed are well known in the art and completelyconventional, and are accordingly not depicted in detail in the drawing.The exceptions are two two-directional shift registers, one of which iscapable of storing R digits and the other of which stores N digits. FIG.7A is a generalized depiction of this type of shift register circuit,and FIG. 7B is a symbolic depiction of the FIG. 7A circuit.

The N-digit two-directional shift register circuit shown in FIG. 7Aincludes N bistable circuits or stages F1 F(I-1), PI, F(I+l) FN, each ofwhich includes set and reset input terminals and l and 0" outputterminals. The N bistable circuits are interconnected by a pluralitty ofAND and OR circuits which are arranged in such a manner that theapplication of a shift forward or 1 signal to lead 700 causes thedigital representation of the register to be shifted one place to theright. For example, as a result of such a signal, the state of thebistable circuit F1 would be transferred to the next bistable circuit F2of the register, the state of the bistable circuit F(I1) would betransferred to the circuit E1, the state of the circuit FI would betransferred to the circuit F(I+1), and so forth, in a conventionalmanner characteristic of shift register circuits. Similarly, theapplication of a shift reverse or 1 signal to lead 705 causes thedigital representation of the register to be shifted one place to theleft.

In a decoder which includes a FIG. 7A type register it is sometimesnecessary, in the process of shifting the representation of the registerto the right or to the left,

. x Equations 4 that a selected one of the stages receive its next-stateinformation from an external source rather than from the stage adjacentthereto. This can be accomplished by applying a blocking signal to aselected one of the leads of the register of FIG. 7A. For example,assume that it is desired to shift the representation appearing in theregister one place to the right, but that the next state of the bistablecircuit FI is to be determined by an external source rather than by thepresent state of the adjacent stage F(I1). The application of a blockingor signal to the lead designated Tl disables both of the AND circuits710 and 715 and thereby prevents the output representations of stageF(I--l) from affecting the state of the stage FI, leaving control of thestate of the stage F1 to whatever signals are applied to the set andreset leads thereof. It is noted that each blocking signal lead normallyhas applied thereto a gating or 1 signal.

Each stage of the shift register circuit illustrated in FIG. 7A includesa plurality of set and reset leads. For example, the stage Fl includesset leads S1, 51A, $18, a 1 signal on any one of these leads beingeifective to maintain or to switch the stage F1 to its 1 state. The 1state of the stage F1 is represented by a 1 signal on its 1 output leadand a 0 signal on its 0 output lead. The stage F1 also includes resetleads, designated R1, RlA. The FIG. 7A circuit also includes a commonreset lead 720 by means of a 1 signal on which every stage of theregister circuit may be maintained at or switched to its 0 state.

The bistable circuits included in the shaft register shown in H6. 7A areof a conventional type, in which the pulses applied thereto need be onlyof a relatively short duration, say, 0.3 microsecond, and in which theoutput indications of the circuits do not start to change until afterthe termination of the applied pulses. Thus, for the case of a 0.3microsecond set signal applied to a circuit which is in its 0 state, theoutput indication of the circuit would not start to change to a lindication for, say, 0.5 microsecond.

Turning now to FIG. 8, there is shown a specific Class-1 decoderembodying the principles of the present invention, the illustrateddecoder being one designed to decode 30- digit redundant words. Thedecoder includes two shift registers of the type shown in FIG. 7A, oneshift register 8% including N or 30 bistable circuits and the other one801 including R or 10 bistable circuits. Also, the illustrated decoderincludes two N-E or 23 digit tapped delay lines, one, the informationdelay line 803, being connected to receive signals from theinformation-carrying line 825, and the other one, the synchronizationdelay line 80 being connected to receive signals from thesynchronization line 850. The decoder also includes a plurality of AND,OR, INVERTING AMPLIFIER, EX- CLUSiVE-OR, and bistable circuits connectedas shown in FlG. 8. Additionally, the FIG. 8 decoder comprises arnultivibrator 805 which after receiving a start pulse on lead 806produces output clock pulses on lead 807 at the same repetition rate asthat of the pulses on the lines 825 and 859, the first output of themultivibrator 805 occurring one digit period after the period in whichthe start pulse occurs. The output sequence on the lead 807 continuesuntil a stop pulse is applied to the multivibrator 8195 via lead 808.

Initially, assume that all the bistable circuits and registers of theFIG. 8 decoder are reset. Then, as a redundant word is received by thedecoder from the noisy transmission channel, the synchronization pulses(one per digit position) are applied to the upper delay line 8.04 andthe information pulses (one per 1 representation) are applied to thelower delay line 803. No other action takes place until 23 consecutivesynchronization pulses are received by the line 804.

In response to the receipt from the channel of the 23rd consecutivesynchronization pulse, bistable circuit 851 is set through AND circuits821 and 822 and from that time on, as long as digits continue to arriveconsecutively from the synchronization line 850, a signal appears at theoutput of the AND circuit 822. The 23rd consecutivelyreceivedsynchronization pulse causes a signal to appear at the output of ANDcircuit 823. This signal gates all the ls appearing in the informationdelay line 803 through 23 two-input AND circuits 802 to the 30-d-igitshift register 800.

All incoming synchronization pulses subsequent to the 1 one appear atthe output of AND circuit 824. The first one of these subsequent pulsesappears at the output of AND circuit 825A and sets bistable circuit 852to its 1 state. The second one of these subsequent pulses appears at theoutput of AND circuit 826 and resets the bistable circuit 852. In thismanner the 24th and all subsequent even-numbered synchronization pulsesappear at the output of the AND circuit 825A, and the 25th and allsubsequent odd-numbered synchronization pulses appear at the output ofthe AND circuit 826. All the pulses which appear at the output of theAND circuit 824 shift the BO-digit shift register 800 forward (i.e., tothe right), while only the odd pulses (i.e., the pulses which appear atthe output of the AND circuit 826) are effective to shift the IO-digitshift register 801 forward. Note that until such time as the absence ofa synchronization pulse on the line 850 is detected, the first threeleft-hand bistable circuits of the 10-digit shift register 801 haveapplied thereto via AND circuit 827 constant set input pulses. Also,note that for each forward shift of the 30-digit shift register 800, thenew value for the extreme left-hand bistable stage of the register 800is derived from tap No. 1 of the information delay line 803 via ANDcircuit 824A.

The end of a consecutively-received sequence of synchronization pulsesis indicated by the absence of a digit pulse at the output of tap No. 1of the synchronization delay line 804 and by the simultaneous presenceof pulses at taps Nos. 2 through 23 of the delay line 804. As a resultof this condition, a pulse appears at the output of AND circuit 828.This pulse sets bistable circuit 853 and starts the multivibrator 805which, as stated above, provides output clock pulses at the repetitionrate characteristic of the pulses on the information-carrying andsynchronization lines. These output pulses from the multivibrator 805pass through AND circuit 820 and shift both of the registers 800 and 801in their reverse directions.

No other action takes place in the decoder shown in FIG. 8 until theIO-digit register 801 has reverse-shifted to such a point that thefourth from the left bistable circuit thereof is reset. At this pointthe stages F1 through F10 of the register 801 respectively contain thedigital representation 1110000000. This representation indicates thatthe desired sequence of NE or 23 digits is located in bistable circuitsF1 through F23 of the 30-digit register 800. At this point in time,internal shifting is blocked at the bistable circuit F23 by a signalwhich is applied to terminal T23 of the register 800 via lead 801A andOR circuit 830, and the new value to be set into F23 for each of thenext three shift pulses comes from the output of the EXCLUSIVE-ORcircuit 870 via AND circuit 831. The inputs to the EXCLUSIVE-OR circuit870 are signals representative of the states of the bistable circuits F1and F21 of the shift register 800. As a result, the next three bacr:shifts place a unique parity check subsequence in the stages F21, F22,and F23 of the register 800, thereby indicating the type of errorpresent in the redundant word received from the noisy transmissionchannel.

Following these three shift pulses, each stage of the IO-digit register801 is in its 0 state. This, in turn, results in (1) the setting ofbistable circuit 853 through AND circuit 832, which primes the decoderfor steps 2 through 5; (2) the deactivation of the AND circuit 831; (3)the activation of AND circuit 833, which allows the generated shiftregister sequence for parity correction to pass from EXCLUSIVE-ORcircuit 871 to the stage F23 1 1 of the shift register 800; (4) theactivation of AND circuit 834, which permits the generated informationdigit derived from EXCLUSIVE-OR circuit 872 to be set into the stage F20of the register 800; and (5) the blocking of internal shifting to thestage F20 of the register 800 by a signal on lead 820 to terminal T20 ofthe register 800.

Reverse-shifting of the 30-digit register 800 continues under thecontrol of output clock pulses applied from the multivibrator 805 vialead 881 to the shift reverse terminal of the register 800, until asignal appears at the output of AND circuit 835, which occurs when theparity subsequence contained in the stages F21, F22, F23 of the register800 is 1, 0, 0, respectively. This condition results in the resetting ofthe bistable circuits 851 and 852 via AND circuit 835 and indicates thatone more shift of the SO-digit register 800 is required. After thisshift, and as a result of the stages F21, F22, F23 respectivelyrepresenting 0, 0, 1, a signal appears at the output of AND circuit 836,which resets the bistable circuit 853. The next output pulse from themultivibrator 805 passes through AND circuit 837 and (1) reverses thestate of the stage F20 of the register 800 through AND circuits 838 and839; (2) resets the bistable circuit 853; and (3) sets bistable circuit855. The next and last pulse from the multivibrator 805 passes throughAND circuit 840 and (1) resets the bistable circuit 855; (2) stops themultivibrator 805; and (3) signals associated circuitry (not shown) viawordready lead 890 that a correct information word is stored in thestages F1 through F20 of the register 800. After the information word isgated out of the register 800, a word-received signal from a suitablesource (not shown) resets the decoder circuit in preparation for thereception of a new word from the noisy transmission channel. Additionaloutput signals, designated Class-1 and stop, appear on leads 891 and892, respectively, and indicate the connections which may be madebetween the Class-1 decoder depicted in FIG. 8 and the Class-2 decodershown in FIG. 14.

Now, to demonstrate in a particularly specific manner theerror-correcting capabilities of the Class-1 decoder shown in FIG. 8,assume that the first three digits of the synchronization wordrepresented in FIG. 6 are lost during transmission. Assume also, for thesake of the example, that the first three digits of the redundantinformation Word are respectively changed in value from 0, 0, 0 to 1,1, 1. These first three digits of each of the redundant andsynchronization words occur in digit positions 1 2 3- In response to theappearance at the taps of the synchronization delay line 804 shown inFIG. 8 of the first 23 consecutive synchronization digits, specifically,the synchronization digits in positions x., through x25, :1 signal isapplied to the AND circuits 802 to gate the information digits inpositions x; through 2: from the information delay line 803 into thestages F1 through F23 of the shift register 800, the digit in position xbeing placed in the stage F23, the digit in position x being placed inthe stage F22, et cetera, with the 23rd digit in position x being placedin the stage F1. The condition of the register 800 is represented inrows 1 and 2 of FIG. 9, row No. 1 indicating the initial representationof the 30 stages of the register 800 and row No. 2 indicating theirrepresentation subsequent to the gating to the stages F1 through F23 ofthe digits in positions x through x of the received redundant word. Notethat each of the information and check digits included in row No. 2 ofFIG. 9 includes thereunder a digit position identifier.

FIG. 10 indicates the various representations which are stored in theIO-digit shift register 801 of FIG. 8 during the decoding operation ofthe herein-described Class-1 system. Row No. 1 of FIG. 10 depicts theinitial representation of the 10-digit register 801, and row No. 2indicates the representation which the register S01 assumes in responseto the application to the synchronization delay line 804 of the 24thconsecutive synchronization digit.

As the synchronization digits in excess of the first 23, viz., thoseappearing in positions 27, x x x continue to be applied to thesynchronization delay line 804, four shift-forward pulses are applied tothe shift register 800 via the AND circuit 824. Additionally, thesynchronization digits appearing in position x and x cause the register801 to be shifted forward two places. Row No. 3 of FIG. 9 indicates theresulting contents of the register 800, and row No. 3 of FIG. 10indicates the resulting contents of the register 801.

As described in detail above, the detection by the delay line 804 of theend of a synchronization digit sequence causes a start signal to beapplied to the multivibrator 805, Whose output clock pulses cause bothof the registers 800 and 801 to shift in a reverse direction until theregister 801 contains the digital representation 1110000000, which islisted in row No. 4 of FIG. 10. It is clear that two shift-reversepulses are required to convert the representation in row No. 3 to thatin row No. 4 of FIG. 10.

The register 800 is also reverse-shifted two places, the resultingrepresentation thereof being indicated in row No. 4 of FIG. 9, thedigits stored in the stages F1 through F23 constituting a centeredsequence of N-E or 23 digits. For the specific example consideredherein, the centered sequence comprises the 23 digits appearing in digitpositions x through x Reverse-shifting of the register 800 continues,and at each of the next three shifts the sum modulo 2 of the digitsappearing in the stages F1 and F21 is inserted into the stage F23. Thefirst such sum is the result of adding x and x and is indicated in rowNo. 5 of FIG. 9. The second such sum is the result of adding x and x andis listed in row No. 6 of FIG. 9, along with the other reverse-shiftedcontents of the register 800. Finally, the third such sum is the resultof adding x and x and is indicated in row No. 7 of FIG. 9.

At this point an sor S-digit subsequence generated by the EXCLUSIVE-ORcircuit 870 is stored in the stages F21, F22, F23 of the shift register800 of the decoder shown in FIG. 8. This subsequence is uniquelypositionable within the sequence 0001011100, which is the outputsequence of the generator 500 of the encoder illustrated in FIG. 5.

In a Class-l decoder of the specific type depicted in FIG. 8, the valueof the 3-digit sequence stored in the stages F21, F22, F23 of the shiftregister 800 may as sume any one of the eight values listed in FIG. 11.The contents of the stages F1 through F20 of the register 800 for eachof the eight possible sequences are also indicated in FIG. 11.Furthermore, FIG. 11 lists for each possible 3-digit sequence the numberof additional shift-reverse pulses which are required to shift thedigits appearing in positions x through x into the stages F 1 throughF20.

For the specific example considered herein, the subsequence has thevalue 111 and the digits stored in the stages F1 through F20 of theregister 800 are the digits which appear in positions x through x of theredundant word. Moreover, five additional reverse-shifts are required toplace the digits appearing in positions x through x in the stages F1through F20 of the register 800. These facts are represented in row No.7 of FIG. 9 and row No. 6 of FIG. 11.

Reverse-shifting of the contents of the register 800 of FIG. 8 continuesunder the control of the multivibrator 805, the EXCLUSIVE-OR circuit 871receiving as inputs thereto the digits stored in the stages F21, F22.The circuit 871 supplies an output 1 signal to the set terminal of thestage F23. Thus, as the register 800 is reverse-shifted, the circuit 871sequentially generates the subsequences which respectively appear inrows 5. 4, 3, and 2 of FIG. 11, each of these subsequences appearing insuccession in the stages F21, F22, F23 of the register 800. Row No. 8 ofFIG. 9 depicts the contents of the register 800 after the first one ofthese additional reverse shifts. and rows 9, 10, 11, and 12 respectivelydepict the 13 register contents after subsequent successive reverseshifts.

The output of the EXCLUSIVE-OR circuit 871 is also applied to one inputterminal of the EXCLUSIVE-OR circuit 872, the other input to the circuit872 being derived from the stage F1 of the register Silt). The output ofthe circuit 872 is applied to the stage F20. In this way, the digitalrepresentation applied to the stage P20 is reconstructed from one digitof the redundant word and one digit of the unique subsequence. Forexample, looking at row No. 8 of FIG. 9, there is indicated the factthat one input to the EXCLUSIVE-OR circuit 8'72 is a signalrepresentative of the state of the stage F23, viz., a signal, which inturn was derived from the modulo 2 sum of x and x The other input to thecircuit 872 is a signal representative of the former state of the stageF1, viz., a 0 signal representative of the digit in posi tion x Hence,by combining in an EXCLUSIVE-OR circuit the digits respectivelyrepresentative of x +x and x the digit in position x is reconstructed.As noted above, this reconstructed information digit is applied to thestage F20 of the register 800.

When the check subsequence stored in the stages F21, F22, F23 of theshift register Stltl assumes the value 100 (which is represented in rowNo. 11 of FIG. 9), the register 800 is reverse-shifted once more, butthe value of the digit inserted into the stage F20 of the register 8% isreversed in value. This modification in the normal pattern of generatingthe subsequences is required in view of the fact that the 000subsequence listed in row No. 1 of FIG. 11 cannot be derived from arecurrence relationship. Subsequent to the reversal of the digitinserted into the stage F20, there is stored in the register 8.0.9 therepresentation listed in row No. 12 of FIG. 9. The digits stored in thestages F1 through F20 of the register 800 are the decoded informationdigits. These digits correspond exactly to the digits appearing inpositions x through x of FIG. 6, despite the fact that the digits inpositions x x x were assumed to have been mutilated during transmission.Hence, the specific example considered herein has demonstrated theerror-correcting capabilities of the illustrative Class-1error-correcting system for one particular type of Class-1 error.

As stated previously hereinabove, Class-2 errors encompass all Class-lor end-connected errors and, in addition, interior loss-bursts of lengthE. An information word can be encoded for Class-2 error-correction byextending the Class-1 parity checking principles to include therequirement that every digit of the informa tion word be included in theformulation of the parity check group to be sufiixed to the informationword. Since each parity check digit must be derived from the same numberof variables, this requirement leads to the necessity for making thenumber n of information digits a multiple k of the number r of digitsincluded in a shift register sequence. Hence, for some integer k,

t is noted that although r is fixed for a given E, values r=r+1, r+2, etcetera, can be formed by using partial shift register sequencesassociated with larger values of E. However, in the interests ofsimplicity and clarity of presentation and because the satisfaction ofEquation 14 results in a minimally redundant Class-2 encoder, it isassumed herein that Equations 14 hold. The encoder equations then becomeA specific illustrative Class-2 encoder for the particular case of nequals 20 and E equals 7 is shown in FIG. 12. This encoder is identicalin configuration and operation to the Class-1 encoder described aboveand depicted in FIG. 5 except for the fact that in the Class-2 encoderthe parity check digit generation process involves the informationdigits stored in two spaced stages, viz.,

14 the first or terminal output stage and the 11th stage, of the mainregister of the encoder.

More specifically, the information digits appearing in the first and11th stages P and F respectively, of the main shift register 119 of theClass-2' encoder of FIG. 12 are combined in an EXCLUSIVE-OR circuit 111,the output of the circuit 111 being applied to one of the inputterminals of the check digit-generating EX- CLUSTVE-OR circuit 130. Inthis way, every one of the 20 information digits, rather than as in theClass-1 case only the first 10 information digits, enters into thedetermination of the 10-digit parity check group which is sufi'ixed tothe information word. Except for this difference, the encoders of FIGS.5 and 12 are. identical.

A Class-2 decoder treats every received sequence which has a length ofat least NE consecutive digits in a manner similar to that describedabove with respect to the decoding operation in a Class-1 system, theonly difference therebetween being that in the Class-2 decoder thegeneration of a parity check subsequence is derived from one check digitand two, rather than only one, information digits. Accordingly, toanalytically describe the decoding operation of a Class-2 system forClass-1 errors, the Class-1 Equations 8, 12 and 13, set forth above mustbe respectively changed to read as follows:

The receipt by the decoder of a Class-2 error-correcting system of aredundant Word which does not include a continuous sequence of at leastN--E digits indicates that the received word includes at least oneinterior lost digit at a distance greater than E digits from one end ofthe received sequence. Such an interior error can be corrected because(1) no shift in the received information word with respect to thesynchronization word has taken place: (2) all spaces or lost digits z inthe received synchronization sequence can be detected; and (3) allinformation digits corresponding to the lost synchronization digits canbe corrected, since each such information digit affects only one of thethree components from which one of the parity checks was derived. Foreach space Z in the synchronization word, the correct valuve of thecorresponding information digit x can be determined from the followingequations:

The Class-2 decoder may be regarded as comprising two parallel-connectedunits, one having the capacity for correcting Class-l errors and being aslightly modified version of the Class-l decoder depicted in FIG. 8, andthe other, shown in FIG. 14, having the capacity for correcting interiorerror bursts. Illustratively, the Class 1 error-correcting unit of theClass-2 decoder may take the form of the Class-1 decoder shown in FIG.8. The only change that need be made in the FIG. 8 decoding arrangementis to break the lead 899 which interconnects the terminal F214 of theshift register 8% and the input terminal 870A of the EXCLUSIVE-ORcircuit 187i and to insert therein another EXCLUSIVE- OR circuit. Tobemore specific and for purposes of a. clear comparison, FIG. 13A showsthe EXCLUSIVE- OR circuit 370 of FIG. 8 and indicates the connectionsmade thereto in the decoder of a Class-1 error-correcting system, whileFIG. 13B shows the circuit 870 and an 15 additional EXCLUSIVE-OR circuit131 and the connections made thereto in the Class-l decoder unit of aClass-2 error-correcting system. With the modification specified in FIG.13B, the FIG. 8 decoder is capable of automatically correcting for anyClass-1 mutilation which occurs to an information Word that is encodedin a Class- 2 encoder.

The presence in a Class-2 system of an interior error burst of length 6Edigits is indicated by the appearance of a signal at the output of ANDcircuit 422 of the specific decoder shown in FIG. 14. For such a signalto appear there, the following four conditions must be met: (1) theremust be a 1 signal at tap No. 30 of synchronization delay line 480; (2)there must be a 1 signal at tap No. l of the line 480; (3) there must beno 1 signal on the synchronization line 850, which is indicated by a 1signal at the output of inverting amplifier 460; and (4) bistablecircuit 471 must have remained reset for at least 26 digit intervals,which is indicated by a 1 signal at the output of noninverting amplifier453.

Condition No. 4 can be restated in terms of the input conditions of ANDcircuit 421, viz., neither detection of (l) a Class-1 error or (2) aninterior error burst of length E digits nor (3) detection of a delay ofat least 8.5 digit intervals between synchronization pulses (which isindicated by the inverting amplifier 460 and network No. 1) should haveoccurred for at least 26 digit intervals.

An understanding of condition No. 4 depends on an understanding of themode of operation of networks 1 and 2 of FIG. 14. The networks operateas follows. When the input to a network is a 1 signal, the capacitor ofthe network is allowed to charge to a positive value, the charging timeconstant thereof being adjusted by an associated variable resistor, theadjustment of which is made such that at a specified time (8.5 digitintervals for network No. l and 26 digit intervals for network No. 2)the output voltage of the network reaches the threshold voltage ofbistable circuit 471 or of the noninverting amplifier 453. This is thepoint at which the logical value of the signal on the output lead of thenetwork changes from a O to a 1. In any digit interval in which theinput lead of a network has a signal applied thereto, there is provideda low impedance discharge path which reduces the voltage on thecapacitor to zero. Charging of the capacitor starts anew after the inputlead of the network assumes the value 1.

The number of digit intervals assigned to each of the networks shown inFIG. 14 is determined by the following factors. Network No. 1 is set for8.5 digit intervals since 8 digit intervals is the longest time thatcould elapse between successive received synchronization pulses on acorrectable Class-2 error, while 9 digit intervals is the shortest timethat could elapse between two transmitted Words. Network No. 2 isadjusted for 26 digit intervals as a center value between 23, theshortest duration, and 30, the longest elapsed time than can occurbetween the detection of the inter-word spacing (by network No. l) andthe detection of a Class-2 error word.

In response to the detection of an interior error, a 1 signal appears atthe output of the AND circuit 422. This 1 signal does the following: (1)sets bistable circuit 472; (2) sets the bistable circuit 471; (3) gatesthe digits stored in information delay line 485 through 30 two-input ANDcircuits 481 into stages F1 through F30 of a 30-digit shift register490; (4) starts multivibrator 475, which thereafter produces outputclock pulses at the repetition rate of the digits received from thesynchronization and information-carrying lines; and sets stages F4, F6,F7, F8 in a IO-digit shift register 495. As a result, the stages F1through F10 of the 10- digit shift register 495 contain, respectively,the digital representation 0001011100, which, it is noted, is exactlythe parity shift register sequence supplied by the generator 100 of theClass-2 encoder shown in FIG. 12.

The decoding operation performed by the circuit arrangement shown inFIG. 14 involves 20 forward (i.e., to the right) shifts of the SO-digitregister 490 and, in synchronism therewith, 20 reverse shifts of the10-digit register 495, the new value of the stage F10 of the register495 being derived from the stage P1 of the register 495 through ANDcircuits 428 and 429. Note that, as in the case of the register 801 ofthe Class-1 decoder illustrated in FIG. 8, the lO-digit shift register495 also performs the function of counting the output clock pulses ofthe multivibrator 475. Specifically, every 10th output pulse from themultivibrator 475 appears at the output of AND circuit 433.

The multivibrator 475 supplies 20 output clock pulses which pass throughAND circuit 424 and do the following: (1) reverse-shift the lO-digitregister 495 via OR circuit 427; and (2) forward-shift the 30-digitregister 490 through OR circuit 426, the new value inserted into thestage F1 of the register 490 being obtained from tap No. 31 of theinformation delay line 485, initially via AND circuits 431 and 431A.This shifting action continues until the first lost synchronizationdigit is detected by inverting amplifier 461 and AND circuit 430. Theresulting 1 signal output of the AND circuit 430 sets bistable circuit474. The shifting action of both registers continues as before, but nowthe new value inserted into the stage P1 of the register 490 is derivedfrom EX- CLUSIVE-OR circuit 445 via AND circuits 432 and 432A. The valueso derived is the correct one for the information digit corresponding inposition to the lost synchronization digit because the information digitis constructed in a manner identical to that employed in the encodingprocess, viz., from the shift register sequence (Fl-1 of the 10-digitregister 495) and from the EX- CLUSIVE-OR circuits 444 and 445, whichare serially connected to FIG-1 and F20-1 of the 30-digit register 490.

In response to the 10th output pulse from the multivibrator 475,bistable circuit 473 is set through AND circuits 433 and 435. Inresponse to the 20th multivibrator pulse, the bistable circuit 473 isreset through AND circuits 433 and 434, thereby causing the resetting ofthe bistable circuits 472 and 474. The next and last pulse from themultivibrator 475 appears at the output of AND circuit 425, therebystopping the multivibrator and signaling to external circuitry by meansof a wordready signal on lead 499 that the corrected information word isavailable in the stages F1 through F20 of the shift register 490. Whenthe corrected word has been received by the external circuitry, there isprovided a pulse from a reset source (not shown) to reset the FIG. 14decoder in preparation for the reception of another redundant word fromthe noisy transmission channel.

It is to be noted that a Class-2 decoder made in accordance with theprinciples of the present invention need not include the two completelyseparate and distinct decoding units described hereinabove. Instead,several of the circuit components of a Class-2 decoder are adaptable todecode either end-connected or interior error bursts, thus makingpossible a considerable reduction in the required amount of decodingcircuitry. For example, two rather than four delay lines are sufficientto accomplish the Class-2 decoding operation. These two lines are: asingle synchronization delay line characterized by a delay of 30 digitintervals and having thereon 30 equally-spaced taps, and a singleinformation delay line characterized by a delay of 31 digit intervalsand having 31 equally-spaced taps. Additionally, a single N'digit shiftregister and a single R-digit shift register can perform the functionsof the four registers described above as being included in the twoseparate units of a Class-2 decoder.

In the case in which the N-digit and Rdigit registers are shared by thetwo units of a Class-2 decoder, each of OR circuits 423, 426, 427 shownin FIG. 14 receives 17 an input signal either from a unit of the FIG. 14arrangement or via leads 140, 141 142, respectively, from the modifiedFIG. 8 arrangement.

It is to be understood that the above-described arrangements areillustrative of the application of the principles of the invention.Numerous other arrangements may be devised by those skilled in the artWithout departing from :the spirit and scope of the invention. Forexample, although emphasis herein has been directed to applying theprinciples of this invention to the correction of errors which occur ona transmission channel that interconnects spaced encoding and decodingunits, it is to be understood that these principles are equallyapplicable to the correction of errors in information processingequipment which is positioned at a single location. Specifically, theprinciples of the present invention are to be understood to apply to thecorrection of errors which occur in the internal circuitry of suchequipment.

What is claimed is:

1. In combination in a self-correcting binary information system whichincludes a transmission channel subject to error bursts, an encodercomprising means for supplyin information digits, means for timing saidsupplying means and for providing synchronization digits, first shiftregister means responsive to the output of said supplying means forserially applying said information digits to said channel, means forgenerating check digits and for serially applying said check digits tosaid first shift register means for application to said channel, saidgenerating means including second shift register means for providing abinary sequence which includes at least one and one 1, said generatingmeans also including modulo 2 adding means successively responsive tothe output of said second shift register means and the information digitappearing in at least one stage of said first shift register means forgenerating said check digits and for serially applying them to saidfirst shift register means, and means for coupling said synchronizationdigits to said channel; and a decoder comprising delay line meansconnected to said transmission channel for receiving therefrom saidinformation and check digits and said synchronization digits, thirdshift register means connected to said delay line means for receivingtherefrom said information and check digits, means for shifting saidinformation and check digits through said third shift register means,and parity reconstruction circuit means connected to said third shiftregister means for regenerating erroneously-received information digitswhich are within the error-correcting capabilities of said system assaid information and check digits are shifte through said third shiftregister means.

2. In combination in a self-correcting binary information system whichincludes a transmission channel subject to error bursts, an encodercomprising means for supplying information digits, means for timing saidsupplying means and for providing synchronization digits, first shiftregister means responsive to the output of said supplying means forserially applying said information digits to said channel, means forgenerating check digits and for serially applying said check digits tosaid first shift register means for application to said channel, saidgenerating means including second shift register means for providing abinary sequence which includes at least one 0 and one 1, said generatingmeans also including modulo 2 adding means successively responsive tothe output of said second shift register means and the information digitappearing in the output stage of said first shift register means forgenerating said check digits and for serially applying them to saidfirst shift register means, and means for coupling said synchronizationdigits to said channel; and a decoder comprising delay line meansconnected to said transmission channel for receiving therefrom saidinformation and check digits and said synchronization digits, thirdshift register means connected to said delay line means for receivingtherefrom said information and check digits, means for shifting saidinformation and check digits through said third shift register means,means'for deriving from said information digits in said third shiftregister means a subsequence of said encoder sequence, means responsiveto the application thereto of said sub-sequence for re'es-tablishingsynchronization between the encoded and decoded information digits, andparity reconstruction circuit means for regeneratingerroneouslyareceived information digits which are within theerror-correcting ca pabilities of said system.

3. In combination in a self-correcting binary information system whichincludes a transmission channel subject to error bursts, an encodercomprising means for supplying information digits, means for timing saidsupplying means and for providing synchronization digits, first shiftregister means responsive to the output of said supplying means forserially applying said information digits to said channeL'means forgenerating check digits and for serially applying said check digits tosaid first shift registermeans for application to said channel, saidgenerating means including second shift register means for providing abinary sequence which includes at least one 0 and one 1, said generatingmeans also including modulo 2 adding means successively responsive tothe output of said second shift register means and the informationdigits appearing in a plurality of spaced stages of said first shiftregister means for generating said check digits and for applying them tosaid first shift register means, and means for coupling saidsynchronization digits to said channel; and a decoder comprising delayline means connected to said transmission channel for receivingtherefrom said information and check digits and said synchronizationdigits, third shift register means connected to said delay line meansfor receiving therefrom said information and check digits, means forshifting said information and check 'digits through said third shiftregister means, means for detecting the presence of an interior errorburst in said received digits, and parity reconstruction circuit meansresponsive to the presence of an interior error burst for regeneratingerroneously-received information digits which are within theerror-correcting capabilities of said system as said information andcheck digits are shifted through said third shift register means.

4. In combination in a self-correcting binary system which includes anoisy transmission channel subject to error bursts, multistage means forstoring an information Word, said multistage storing mean-s including aterminal output stage connected to said channel and further including aninput stage, means for serially shift ing the digits of said informationword through said multistage means to said channel, means responsive-tosaid shifting means and to the information successively stored in atleast one of the stages of said multistage means for generating a paritycheck group whose "digits respectively establish both even and oddparity relationships with respect to said information digits and forserially applying the digits of said group to the input stage of saidmultistage means, thereby to sufiix said group :to said word.

5. A combination as in claim 4 wherein said gener ating and applyingmeans includes a first modulo 2 adder having an output terminal, andmeans interconnecting said output terminal and said input stage of saidmultistage storing means.

6. A combination as in claim 5 wherein said go crating and applyingmeans further includes means connected to one input terminal of saidfirst modulo 2 adder for supplying thereto a shift register sequencewhich includes at least one 0 and one 1.

7. A combination as in claim 6 wherein said first modulo 2 adderincludes another input terminal, and means interconnecting said otherinput terminal and at least one stage of said multistage storing means.

8. A combination as in claim 7 wherein said means interconnecting saidother input terminal of said modulo 2 adder and at least one stage ofsaid multistage storing means includes a direct electrical connectionbetween said other input terminal of said first modulo 2 adder and theterminal output stage of said multistage storing means.

9. A combination as in claim 7 wherein said means interconnecting saidother input terminal of said modulo 2 adder and at least one stage ofsaid multistage storing means includes a second modulo 2 adder havingtwo input terminals respectively connected to spaced stages includingsaid terminal output stage of said multistage storing means, said secondmodulo 2 adder having an output terminal, and means connecting saidoutput terminal of said second modulo 2 adder to the other inputterminal of said first modulo 2 adder.

10. In combination in a system for redundantly encoding an informationword by sutfixing thereto a parity check group, multistage shiftregister means for storing an information word, means for generating anoutput sequence which includes at least one and one 1, means connectedto said shift register means and to said generating means for applyingshift pulses thereto, and modulo 2 adding means responsive to the outputof said generating means and to the state of at least one of the stagesof said shift register means for generating a parity check group and forapplying said group to the input stage of said shift register means.

11. In combination in a system for redundantly encoding an informationword by suffixing thereto a parity check group, multistage shiftregister means for storing an information word, means for generating anoutput sequence which includes at least one 0 and one 1, means connectedto said shift register means and to said generating means for applyingshift pulses thereto, and modulo 2 adding means responsive to the outputof said generating means and to the state of the output stage of saidshift register means for generating a parity check group and forapplying said group to the input stage of said shift register means.

12. In combination in a system for redundantly encoding an informationword by suffixing thereto a parity check group, multistage shiftregister means for storing an information word, means for generating anoutput sequence which includes at least one 0 and one 1, means connectedto said shift register means and to said generating means for applyingshift pulses thereto,

and modulo 2 adding means responsive to the output of said generatingmeans and to the states of a plurality of spaced stages of said shiftregister means for generating a parity check group and for applying saidgroup to the input stage of said shift register means.

13. A combination as in claim 12 wherein said modulo 2 adding meansincludes a first modulo 2 adder responsive to the states of a pluralityof spaced stages includ ing the terminal output stage of said shiftregister means, and a second modulo 2 adder responsive to the output ofsaid first adder and to the output of said generating means for applyingsaid parity check group to the input stage of said shift register means.

14. In combination in a decoding system which is connected to a noisytransmission channel for receiving therefrom an N-digit synchronizationword and an N-digit redundant information word, first tapped delay linemeans for receiving from said channel the digits of a synchronizationword, second tapped delay line means for receiving from said channel thedigits of a redundant information word, N-stage shift register means,normallydisablcd gating means respectively interconnecting the taps ofsaid second delay line means and selected ones of the stages of saidshift register means, means responsive to synchronization digit signalsappearing at selected ones of the taps of said first delay line meansfor applying an enabling signal to said gating means to gate informationdigit signals appearing at the taps of said second delay line means tosaid shift register means, means for sequentially shifting the contentsof said shift register means, and parity reconstruction circuit meansconnected to said shift register means for regeneratingerroneously-received information digits which are within theerror-correcting capabilities of said system as said information digitsignals are shifted through said shift register means.

15. A combination as in claim 14 wherein each of said first and secondtapped delay line means includes N-E equally spaced taps, where E is themaximum number of digits which are affected by an error burst that iswithin the error-correcting capabilities of said decoding system, andwherein said enabling signal applying means responds only to thesimultaneous occurrence of synchronization digit signals at every one ofthe NE taps of said first delay line means to gate the information digitsignals appearing at the NE taps of said second delay line means to saidshift register means.

16. A combination as in claim 15 wherein said shifting andreconstructing means includes modulo 2 adding means for generating asubsequence of the sequence in accordance with which said redundantinformation was originally formed and for deriving from said subsequenceerroneously-received information digits.

17. In combinadon in a decoding system which is adapted to receive anN-digit word from a noisy transmission channel that is subject toend-connected and interior error bursts, means for receiving said wordfrom said channel and for detecting whether said word was subjected toan end-connected or an interior error burst, said detecting meansincluding first delay line means for receiving said word from saidchannel, said first delay line means being characterized by I-J'E digitperiods of delay and having thereon NE equally spaced taps, where E isthe maximum number of digits which are afiected by an error burst,second delay line means for receiving said Word from said channel, saidsecond delay line means being characterized by N periods of delay andhaving a tap at each end thereof, means responsive to signals appearingat the NE taps of said first delay line means for indicating thepresence of an endconnected error burst, and means responsive to signalsappearing at the end taps of said second delay line means and to theabsence of a signal on said channel for indicating the presence of aninterior error burst.

References Cited in the file of this patent Green et al.: An ErrorCorrecting Encoder and Decoder of High Efficiency, Proceedings of theI.R.E., October, 1958 (4 pages).

1. IN COMBINATION IN A SELF-CORRECTING BINARY INFORMATION SYSTEM WHICHINCLUDES A TRANSMISSION CHANNEL SUBJECT TO ERROR BURSTS, AN ENCODERCOMPRISING MEANS FOR SUPPLYING INFORMATION DIGITS, MEANS FOR TIMING SAIDSUPPLYING MEANS AND FOR PROVIDING SYNCHRONIZATION DIGITS, FIRST SHIFTREGISTER MEANS RESPONSIVE TO THE OUTPUT OF SAID SUPPLYING MEANS FORSERIALLY APPLYING SAID INFORMATION DIGITS TO SAID CHANNEL, MEANS FORGENERATING CHECK DIGITS AND FOR SERIALLY APPLYING SAID CHECK DIGITS TOSAID FIRST SHIFT REGISTER MEANS FOR APPLICATION TO SAID CHANNEL, SAIDGENERATING MEANS INCLUDING SECOND SHIFT REGISTER MEANS FOR PROVIDING ABINARY SEQUENCE WHICH INCLUDES AT LEAST ONE "O" AND ONE "1", SAIDGENERATING MEANS ALSO INCLUDING MODULO 2 ADDING MEANS SUCCESSIVELYRESPONSIVE TO THE OUTPUT OF SAID SECOND SHIFT REGISTER MEANS AND THEINFORMATION DIGIT APPEARING IN AT LEAST ONE STAGE OF SAID FIRST SHIFTREGISTER MEANS FOR GENERATING SAID CHECK DIGITS